This invention relates to a semiconductor device, a semiconductor device design method, a recording medium recording a program for executing the semiconductor device design method, and a semiconductor device design support system and in particular to a semiconductor device, a semiconductor device design method, a semiconductor device design method recording medium, and a semiconductor device design support system capable of preventing antenna damage caused by an antenna effect occurring in a plasma step at the metal wiring formation time in a semiconductor process.
In recent semiconductor process wiring steps, various plasma techniques have been used. The representative plasma techniques include dry etching at the wiring layer patterning, plasma TEOS film deposition of wiring layer insulating film in a multi-layered wiring step, and the like, for example, which will be hereinafter referred to as plasma steps.
For example, when plasma etching is executed, if a diffusion layer does not connect to metal wiring, plasma charges accumulate in the metal wiring and an electric current flows into the gate oxide film of the transistor to which the metal wiring connects. The current causes such trouble of destruction of the gate oxide film, change in the transistor characteristics because of film quality change of the gate oxide film, or degradation of the hot carrier life. Such phenomena are called xe2x80x9cantenna effectxe2x80x9d and trouble caused by the antenna effect will be hereinafter referred to as xe2x80x9cantenna damagexe2x80x9d. This antenna damage is also caused by the antenna effect due to side walls of the metal wiring. In order to simplify the explanation, only areas of the metal wirings are taken into consideration.
Such antenna damage proceeds toward the worse when micro-miniaturization develops; the factors are as follows:
First, the gate oxide film itself of a transistor becomes thin and pressure resistance of the gate oxide film considerably lowers as compared with the conventional process. There is an estimation that as the film is furthermore thinned, the antenna damage is remedied because the tunnel current in the gate oxide film grows. However, it is said that antenna rule proceeds toward the worse until at least the gate oxide film thickness of about 5 nm generally used with CMOS according to 0.25-xcexcm design rule.
Second, the minimum gate width reduces the micro-miniaturization of process, micro-miniaturization of process develops, because the signal wiring length does not lessen if the chip size set considering yield, etc., is micro-miniaturized to about 10 mm square.
Third, although damage caused by plasma entering from a side wall of wiring at the over-etching in a dry etching step of wiring is the main factor of the antenna damage, if the wiring width is thinned, the wiring film thickness cannot be so thinned for the purpose of providing resistance to electro-migration of wiring and suppressing the resistance value.
Fourthly, as the wiring pattern becomes fine, the plasma density at the etching time also tends to rise.
Because of the factors as described above, if the antenna ratio is about several thousands in the recent fine process, antenna damage such as destruction of a gate oxide film or characteristics degradation of a transistor has occurred during the manufacturing process in extremely general designed LSI although no problem arises even in the antenna ratio of about a hundred thousand in the conventional CMOS generation, etc., according to 0.8 xcexcm design rule. The xe2x80x9cantenna ratioxe2x80x9d generally refers to the ratio between the area of a gate oxide film and the area of a conductive layer in which plasma charges occurring at the plasma etching time are accumulated.
Against the backdrop, it becomes necessary to take countermeasure against electrostatic destruction in the chip considering a wafer diffusion step apart from ESD protection on packaging and handling required for conventional I/O pins.
The above-described xe2x80x9cantenna ratio of about several thousandsxe2x80x9d means that design considering the antenna damage is required not only for a long pattern such as a power supply, but also in general signal wiring in LSI. This is shown using general values of the current process.
For example, assuming that the area of a gate oxide film portion, namely, gate length X gate width is 0.25 xcexcmxc3x970.6 xcexcm and that the wiring width is 0.4 xcexcm and applying the antenna rule of xe2x80x9cassuming wiring with antenna ratio=3000 or more to be an error,xe2x80x9d the allowed wiring length becomes 1125 xcexcm. However, in the antenna ratio calculation, the conductive layer area in which plasma charges are accumulated is calculated as the area of wiring only.
Therefore, to use such metal wiring running on one side of the chip of LSI having a chip size of 10 mm square as described above, the antenna rule is applied and the metal wiring becomes antenna wiring that can cause antenna damage. However, this does not mean that whenever such as antenna ratio is applied, antenna damage occurs. If a diffusion layer connects to the target wiring in a plasma step, plasma charges escape via the diffusion layer, thus antenna damage does not occur in the gate oxide film; this fact also need to be considered. This means that is an aluminum pattern with the gate oxide film connecting to long aluminum wiring, not connected to the diffusion layer exists, an antenna rule error occurs.
Next, how antenna damage, namely, an antenna rule error occurs in the actual LSI design and specific examples of conventional countermeasure to be taken when the antenna damage, namely, an antenna rule error occurs will be discussed.
First, specific examples of comparatively easy countermeasures against antenna image are given. FIG. 16 is a schematic diagram to show a state in which an unused input pin in a functional block is connected to a power supply trunk and potential is fixed. In the figure, in a functional block 2101 such as RAM or ROM, a second metal input pin 2102 unused is connected via first metal wiring 2103 to a second metal power supply trunk 104 is connected to a third metal power supply trunk 105. When the second metal is etched in a wiring step of such configured LSI, the third metal power supply trunk 105 does not yet exist. Thus, the second metal power supply trunk 104 becomes giant antenna wiring in a floating state not connected to a diffusion layer with respect to a gate oxide film connected to the second metal input pin 2102 unused.
Available as the countermeasures to be taken when such an antenna error occurs are a method of adding an antenna protection diode as shown in FIGS. 17A or 17B to the second metal power supply trunk 104 of the antenna wiring or the first metal wiring 2103, a method of changing the first metal wiring 2103 to third metal wiring, and the like.
If an antenna protection diode is added according to the first countermeasure, plasma charges escape through a diffusion layer of the protection diode as described above, so that occurrence of antenna damage is eliminated. FIG. 17A is a schematic representation to show the structure of an n+ diffusion layer-P well type antenna protection diode 2201 consisting of an n+ diffusion layer 2202 and a P well 2203 fixed to power supply potential VSS and FIG. 17B is a schematic representation to show the structure of a p+ diffusion layer-N well type antenna protection diode 2211 comprising of a p+ diffusion layer 2212 and an N well 2213 fixed to power supply potential VDD.
If the first metal wiring 2103 is changed to third metal wiring according to the second countermeasure, the functional block 2101 and the second metal power supply trunk 104 are separated at the etching time of the second metal forming the second metal power supply trunk 104, thus antenna damage cannot occur.
If an unused input pin is fixed in a normal block formed of a standard macro cell, usually it is fixed to a power supply in the macro cell or a power supply trunk to which the power supply in the macro cell is connected. Since the power supply in the standard macro cell is provided with a substrate contact almost beyond doubt, a path to a well via a diffusion layer exists. Thus, in such a block formed of a standard cell, antenna damage in an unused input pin with potential fixed can little occur.
Next, a specific example of signal wiring harder to counter antenna damage will be discussed with reference to FIGS. 18A to 18C. FIG. 18A is a schematic diagram to describe a layout of signal wiring from one inverter 2301 to another inverter 2302.
In an automatic placement wiring tool, normally longitudinal and lateral wiring layers assigned are used for wiring without considering an antenna rule as described above. Assume that one signal wiring is laid out as first metal wiring 2312 which is very long exists, as shown in FIG. 18A. That is, it is a wiring layout using first metal wiring 2311, 2312 and second metal wiring 2321.
In the layout in FIG. 18A, it seems that antenna damage does not occur because a drain diffusion layer or a transistor in the inverter 2301 is connected to the signal wiring. However, it should be noted that when the first metal wiring 2312 is etched, the second metal wiring 2321 does not exist. That is, the drain diffusion layer of the inverter 2301 is not connected to the first metal wiring 2312, which is long and becomes wiring that can cause antenna damage for a transistor gate oxide film of the inverter 2302. specifying use of upper layer wiring 2541 such as second or third metal as the first metal wiring 2312 in FIG. 18A and again performing automatic wiring processing, as shown in FIG. 19B, and the like, for example.
If an antenna protection diode is added according to the first countermeasure, plasma charges escape through a diffusion layer of the protection diode as described above, so that occurrence of antenna damage is eliminated. The antenna protection diode may be an n+ diffusion layer-P well type antenna protection diode 2303 as shown in FIG. 18B or a p+ diffusion layer-N well type antenna protection diode 2304 as shown in FIG. 18C; it may be designed to apply a reverse bias to a signal line to which the protection diode is connected so that no problem occurs on the operation if the potential level of the signal line changes to high or low. To be precise, if the antenna protection diode is added, the load of the signal line becomes heavy because diffusion capacitance is added. However, if diodes are embedded on mask operation all in wiring that can cause an antenna error, a wiring load problem arises; a load capacitance problem hardly occurs if a contact of the minimum size is added or so.
If a wiring route passing through the diffusion layer wiring 2503 is provided at an intermediate point of the first metal wiring 2312 in FIG. 18A according to the second countermeasure, plasma charges escape through the diffusion layer, so that occurrence of antenna damage is eliminated. FIG. 19A shows an example of using an n+ diffusion layer formed on a P well fixed to power supply potential VSS.
Further, if use of the third metal wiring 2541 as the first metal wiring 2312 is specified and automatic wiring processing is again performed, as shown in FIG. 19B, according to the third countermeasure, at the etching time of the second metal forming the second metal wiring 2321, the second metal wiring 2321 and the gate oxide film of the inverter 2302 are separated and the diffusion layer of the inverter 2301 is connected to the second metal wiring 2321, thus antenna damage cannot occur.
However, the above-described conventional countermeasures taken when antenna damage or an antenna rule error occurs involve the following problems:
First, throughout all the countermeasure, an additional correction to an antenna error is required and when an attempt is made to use a CAD tool for automation, a clear and effective procedure does not exist. That is, an antenna rule error is frequently found at a one-chip wiring layout stage close to the end of design and the current automatic placement wiring tool of CAD does not provide a function for avoiding an antenna rule error. Therefore, with the current state of the art, the designer manually takes such measures of adding an antenna protection diode to a device for which an error is found at the stage where a mask order is about to be given. Such a relapse in the design stage and occurrence of manual work become the largest problem in design automation.
The second countermeasures (see FIG. 19A) involves a performance problem. This means that to provide a wiring route passing through the diffusion layer at an intermediate point of metal wiring, a large resistance value is added as compared with the metal wiring owing to the diffusion layer, worsening the circuit operating speed. If the process is a silicide process, such worsening of the circuit operation speed is a little alleviated.
A common problem to the first and second countermeasures is to place limitations on a design style. In recent years, a technique of executing steps in parallel with layout design as much as possible has been adopted for shortening the time from LSI design to manufacturing. For example, at completion of a chip at the block level, if the blocks are placed and a mask order is given from the ground and diffusion is started on one hand and layout design is furthermore advanced and an antenna rule error is found in the later layout design using aluminum wiring on an upper layer on the other hand, the error cannot be handled by changing the design of the lower layer.
In such a case, the error has to be avoided by changing wiring; a limitation is placed so as to use upper layer metal in place of the metal wiring where the antenna rule error occurs, for example. In this case, the wiring is connected to the diffusion layer at the wiring etching stage and the antenna rule error is solved. However, if the error occurrence frequency increases, wiring corrections as countermeasures against the antenna rule errors are made to the device with wiring well laid out, largely changing the congestion degree of the upper layer aluminum wiring and the wiring pattern. Then, when the wiring is again executed, it cannot be fitted as the same area as before the antenna rule error corrections are made is held, or the wiring congestion degree and the wiring length are changed, thus new trouble of occurrence of a timing error on logical circuit design not previously occurring is caused.
In the recent LSI design, signals whose wiring delay is to be suppressed have been wired at gentle pitches with thick metal film wiring of an upper layer as much as possible; an increase in the congestion degree of the upper layer wiring is undesirable for speed performance.
It is therefore an object of the invention to provide a semiconductor device, a semiconductor device design method, a semiconductor device design method recording medium, and a semiconductor device design support system capable of preventing antenna damage caused by an antenna effect occurring in a plasma step at the metal wiring formation time in a semiconductor process.
It is another object of the invention to provide a semiconductor device, a semiconductor device design method, a semiconductor device design method recording medium, and a semiconductor device design support system that can handle antenna damage or an antenna rule error at high speed and precisely by automatic processing of a CAD tool, etc., if the antenna damage or antenna rule error occurs.
It is still another object of the invention to provide a semiconductor device, a semiconductor device design method, a semiconductor device design method recording medium, and a semiconductor device design support system that can take countermeasures against antenna damage or an antenna rule error with upper layer metal wiring as much as possible by automatic processing of a CAD tool, etc., if the antenna damage or antenna rule error occurs, and resultantly can handle the antenna damage or antenna rule error with small-scale change so that the operation timing on logical circuit design does not largely change before and after the countermeasures are taken.
According to a first aspect of the invention, there are provided a semiconductor device, a semiconductor device design method, a semiconductor device design support system, wherein as cells, etc., to be registered in a cell library, etc., registration step (registration means) previously registers a first cell, etc., having a first conduction type diode comprising a first conduction type diffusion layer connected to an input pin of the cell, etc., and a second conduction type well connected to a second power supply or a second conduction type diode comprising a second conduction type diffusion layer connected to the input pin and a first conduction type well connected to a first power supply and a second cell, etc., not containing the first or second conduction type diode and comprising the same logic as and the same drive capability as the first cell, etc., determination step (determination means) determines whether or not a wiring conductor conducting to the input pin and a gate electrode becomes an antenna ratio exceeding an allowed antenna ratio in the semiconductor device when the antenna ratio is a ratio between the area of the wiring conductor conducting to the gate electrode and the area of the gate electrode, and selection step (selection means) selectively uses the first cell, etc., if the input pin conducts to the gate electrode exceeding the antenna ratio.
That is, after execution of automatic placement and wiring, replacement of cells, etc., occurs. However, a protection diode is added only to a node requiring a countermeasure against occurrence of possible antenna damage or a possible antenna rule error, thus an increase in the semiconductor device area is suppressed and extra protection diodes are not formed; an increase in the parasitic load capacitance of wiring can be suppressed accordingly and as a result, the signal propagation delay time can be shortened and the power consumption of the semiconductor device can be decreased.
According to a second aspect of the invention, there are provided a semiconductor device, a semiconductor device design method, a semiconductor device design method recording medium, and a semiconductor device design support system, wherein as cells, etc., to be registered in a cell library, etc., registration step (registration means) registers repeater cells each having a buffer or an inverter and a first conduction type diode comprising a first conduction type diffusion layer connected to an input pin of the buffer or the inverter and a second conduction type diode comprising a second conduction type diffusion layer connected to the input pin and a first conduction type well connected to a first power supply, determination step (determination means) determines whether or not a wiring conductor conducting to a gate electrode in the semiconductor device exceeds an allowed antenna ratio in the semiconductor device when the antenna ratio is a ratio between the area of the wiring conductor conducting to the gate electrode and the area of the gate electrode, and insertion step (insertion means) inserts one or more repeater cells into any point of the wiring conductor if the wiring conductor exceeds the allowed antenna ratio. Preferably, the register cell comprises two buffers or inverter connected in series and the output buffer or inverter has a larger drive capability than the input buffer or inverter.
Thus, a long wiring conductor where it is feared that antenna damage or an antenna rule error may occur is divided by inserting one or more repeater cells, whereby the signal propagation delay of the wiring is suppressed (first advantage). As the length of the wiring is shortened, antenna damage can be suppressed (second advantage). Further, a protection diode is added to an input pin of a repeater cell, whereby an antenna rule error does not occur for the divided metal wiring connected to the repeater cell (third advantage).
According to a third aspect of the invention, there are provided a semiconductor device, a semiconductor device design method, a semiconductor device design method recording medium, and a semiconductor device design support system, wherein a substrate contact containing a first conduction type diffusion layer and a conduction type well or a substrate contact containing a second conduction type diffusion layer and a second conduction type well is produced so that an unused input pin of the cells, etc., is brought into conduction to a first or second power supply via the substrate contact, whereby a path flowing into the diffusion layer is provided even in the configuration to which a protection diode is not added. Thus, to connect an unused pin to a power supply trunk and fix the potential of the unused pin, an antenna rule error is not caused. Since it leads to stabilization of the well potential, noise resistance, latch-up resistance, and the like of the semiconductor device are also improved.
According to a fourth aspect of the invention, there are provided a semiconductor device, a semiconductor device design method, a semiconductor device design method recording medium, and a semiconductor device design support system, wherein each wiring conductor conducting to a gate electrode in each of the wiring layers, when a ratio between the area of the wiring conductor conducting to the gate electrode and the area of the gate electrode is assumed to be an antenna ratio, is limited to an area or wiring length such that the wiring conductor becomes an antenna ratio of less than a half an antenna ratio allowed essentially in the semiconductor device and is divided into at least three parts for wiring. Thus, the length of wiring continuously running in the same wiring layer is limited to less than a half the original antenna rule value and is divided into at least three parts, whereby wiring forcibly is changed, namely, long wiring can be divided, whereby the antenna ratio of wiring can be suppressed and resultantly, the number of antenna error occurrences can be decreased.
According to a fifth aspect of the invention, there are provided a semiconductor device design method, a semiconductor device design method recording medium, and a semiconductor device design support system, wherein registration step (registration means) defines a position where a first conduction type diffusion layer and a contact can or cannot be placed on a second conduction type well or a position where a second conduction type diffusion layer and a contact can or cannot be placed on a first conduction type well as shape data of each of the cells, etc., to be registered in a cell library, etc., determination step (determination means) determines whether or not a wiring conductor conducting to a gate electrode in the semiconductor device exceeds an allowed antenna ratio in the semiconductor device when the antenna ratio is a ratio between the area of the wiring conductor conducting to the gate electrode and the area of the gate electrode, and insertion step (insertion means) selectively inserts a first conduction type diode or a second conduction type diode if the wiring conductor exceeds the allowed antenna ratio.
Thus, to automatically insert a protection diode, it is not necessary to determine the placement position of the protection diode while seeing various related layers of a diffusion area, polysilicon, etc., in a CAD (computer aided design) system, so that the processing amount in the CAD system may be very light.
According to a sixth aspect of the invention, there are provided a semiconductor device, a semiconductor device design method, a semiconductor device design method recording medium, and a semiconductor device design support system, wherein determination step (determination means) determines whether or not a wiring conductor conducting to a gate electrode in the semiconductor device and having long wiring in an ith wiring layer exceeds an allowed antenna ratio in the semiconductor device when the antenna ratio is a ratio between the area of the wiring conductor comprising to the gate electrode and the area of the gate electrode; and if the wiring conductor exceeds the allowed antenna ratio, insertion step (insertion means) cuts the long wiring in the ith wiring layer in the proximity of the gate electrode and forms the wiring conductor by connecting a short wiring conductor in the ith wiring layer from the gate electrode to the cut point and a long wiring conductor in the ith wiring layer ahead the cut point by a bridge wiring conductor of a length as long as the least two grids in a jth wiring layer of an upper layer above the ith wiring layer (i less than jxe2x89xa6n).
Thus, effective countermeasure against an antenna rule error can be taken. For example, the long wiring in the ith wiring layer causing an antenna rule error before a bridge wiring conductor is placed in the (i+l)th wiring layer is disconnected from the gate electrode at the etching time of wiring of the ith wiring layer by connecting via the bridge wiring conductor in the (i+l)th wiring layer and therefore complete countermeasures against an antenna rule error can be taken. It is feared that bridge wiring may be unable to be used for the top layer because a wiring layer does not exist on the top layer. However, when top layer wiring is etched, a desired circuit configuration is almost accomplished, thus a buffer diffusion layer for driving signal wiring is connected to all long wiring conductors and there is no antenna damage in the wiring formation step of the top layer.
That is, in the invention, if two empty grids of wiring exist in the jth wiring layer of an upper layer (or if two empty grids can be generated), antenna damage or an antenna rule error can be prevented from occurring and the point where bridge wiring is placed is determined by finding an area from the side near the gate electrode of long wiring, so that occurrence of antenna damage caused by the remaining wiring leading to the gate electrode side after the long wiring is cut by the bridge wiring can also be suppressed. Further, basically (unless empty grids are forcibly provided), empty grids of wiring in the jth wiring layer are used, thus a large move of any other wiring little occurs, the whole layout little changes before and after the bridge wiring countermeasure against an antenna rule error is taken, the signal timing change on a large logical circuit does not occur either. Since only an upper wiring layer is used, if an mask order is started in order from the bottom in parallel with layout design to shorten the design period, a wiring layout of upper wiring layers can be handled easily to deal with the antenna rule.
According to a seventh aspect of the invention, there are provided a semiconductor device design method, a semiconductor device design method recording medium, and a semiconductor device design support system, wherein in the insertion step (insertion means), finding step (search means) finds an area of two or more contiguous empty grids in the jth wiring layer overlapping the long wiring in the ith wiring layer from the side near the gate electrode relative to the long wiring in the ith wiring layer and determines insertion of the bridge wiring conductor into the found area.
Thus, the bridge wiring countermeasure against an antenna rule error provided by the insertion step (insertion means) can be efficiently built in the design support system for use. As the bridge wiring is installed, change is only made to a wiring layout of a structure wherein only the two-grid wiring of the long wiring originally existing in the ith wiring layer is lifted up to the jth wiring layer above the ith wiring layer, thus the total wiring length of the signal wiring, the parasitic additional capacitance existing between the signal wiring and any other wiring, and the like little change. Further, the bridge wiring requires at least two via electrodes to make connection between the ith and jth wiring layers and two-via electrode resistance is added to the signal wiring, but can be almost ignored. Thus, the signal timing on the logical circuit, etc., little changes before and after the countermeasures against an antenna rule error are taken. This eliminates such former inefficient design procedure repeating corrections between the normal layout design and design of the countermeasures against an antenna rule error.
According to an eighth aspect of the invention, there are provided a semiconductor device design method, a semiconductor device design method recording medium, and a semiconductor device design support system, wherein if the finding step (search means) cannot determine an insertion area, the insertion step (insertion means) finds a first area of an empty grid in the jth wiring layer overlapping the long wiring in the ith wiring layer from the side near the gate electrode relative to the long wiring in the ith wiring layer, sets a position of the ith wiring layer overlapping the first area to a cut point of the long wiring, moves a long wiring conductor ahead the cut point in the ith wiring layer to another empty area containing a second area in the jth wiring layer overlapping the cut point after the move, and adopts a wiring conductor spread over the first and second areas as the bridge wiring conductor in the jth wiring layer. Thus, even if two or more contiguous empty grids of wiring do not exist in the jth wiring layer of an upper layer, if a first area of an empty grid in the jth wiring layer, an area to which the wiring conductor ahead the cut point in the ith wiring layer can be moved, and a second area of an empty grid in the jth wiring layer can be found, antenna damage or an antenna rule error can be reliably prevented from occurring.
According to a ninth aspect of the invention, there are provided a semiconductor device design method, a semiconductor device design method recording medium, and a semiconductor device design support system, wherein if the finding step (search means) cannot determine an insertion area, the insertion step (insertion means) finds a first area of an empty grid in the jth wiring layer overlapping the long wiring in the ith wiring layer from the side near the gate electrode relative to the long wiring in the ith wiring layer, inserts the bridge wiring conductor in the jth wiring layer to a second area of a length as long as at least two grids from the first area, and again wires wiring conductor in the ith wiring layer overlapping the second area. Thus, even if two or more contiguous empty grids of wiring do not exist in the jth wiring layer of an upper layer, if a first area of an empty grid in the jth wiring layer can be found, antenna damage or an antenna rule error can be reliably prevented from occurring. Since the wiring layout is corrected as the wiring is shifted as a whole, the layout of the wiring conductors is not largely changed and the operation timing, etc., little changes before and after the countermeasure against an antenna rule error is taken.
According to a tenth aspect of the invention, there are provided a semiconductor device design method, a semiconductor device design method recording medium, and a semiconductor device design support system, wherein if the finding step (search means) cannot determine an insertion area, the insertion step (insertion means) finds a first area and a second area which are discontiguous and contain each an empty grid in the jth wiring layer overlapping the long wiring in the ith wiring layer from the side near the gate electrode relative to the long wiring in the ith wiring layer and inserts a bridge wiring conductor in a kth wiring layer above the jth wiring layer (j less than kxe2x89xa6n) between the first and second areas. Thus, even if two or more contiguous empty grids of wiring do not exist in the jth wiring layer of an upper layer, if two empty areas can be found, the kth wiring layer can be used to install bridge wiring.